The present invention relates to a method of verifying a program operation in a non-volatile memory device.
Recently, the demand has increased for a non-volatile memory device which electrically programs and erases data, and does not require a refresh function of periodically rewriting data.
The non-volatile memory device performs a program operation and an erase operation by changing a threshold voltage of a memory cell through moving of electrons by high electric field applied to a thin oxide film.
The non-volatile memory device includes generally a memory cell array, in which memory cells for storing data are disposed in matrix shape, and a page buffer for programming data in a specific memory cell of the memory cell array or reading data from a certain memory cell.
The page buffer has a pair of bit lines connected to a corresponding memory cell, a register for storing temporarily data to be programmed in the memory cell array or data read from a given memory cell, a sensing node for sensing voltage level of a specific bit line or a certain register, and a bit line select circuit for controlling connection of the bit line and the sensing node.
The memory cell may store various different states, and thus a threshold voltage of the memory cell should be increased depending on the states through a program operation.
In case that the same program voltage is applied, the threshold voltage is theoretically increased by the same level. However, since the memory cells do not have uniform characteristics, a memory cell may be programmed more rapidly than the other memory cells or a memory cell may be programmed more slowly than the other memory cells.
In case of programming the memory cell in accordance with an incremental step pulse program (ISPP) method, a program pulse is continuously applied to a corresponding word line until every memory cell is programmed to a voltage more than desired threshold voltage. Hence, in case that a memory cell having a slow program speed exists, the time to be taken for the program operation may be increased. Accordingly, in case that a memory cell has a slow program speed, a time for the program operation should be reduced.
The above information disclosed in this related art section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.